1. Field of the Invention
Embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a semiconductor memory device having a plurality of sense amplifiers which output a plurality of sense amplification enable signals.
2. Description of the Related Art
A semiconductor memory device uses a sense amplifier which receives a small signal to determine a voltage or current level and transmits it to an output pin in order to read data stored in a memory cell.
A sense amplifier having one terminal or a plurality of terminals is conditionally used to properly detect read data stored in a memory cell, and in most cases, the final output terminal of the sense amplifier uses a clocked regenerative amplifier using a positive feedback characteristic since the final output of the sense amplifier should have a power voltage or ground voltage level.
The clocked regenerative amplifier has an advantage in a self amplifying function in that an output signal of a power voltage level and a ground voltage level can be generated in a relatively short time when an enable signal transitions to a high level even in a case where an input signal of a relatively small voltage level is applied.
On the other hand, the clocked regenerative amplifier has a disadvantage in that if error data are applied at a point in time when an enable signal transitions to a high level, a full latch form cannot change them properly them to accurate data, and a semi latch form can possibly change them to accurate data, but it can take a long time for this transition to accurate data.
For the foregoing reasons, the clocked regenerative amplifier can be used in contemporary semiconductor memory devices as a sense amplifier, since a high manufacturing yield can be achieved to ensure that a sense amplification enable period maintains a sufficient margin until a stable input signal is guaranteed.
However, if the sense amplification enable time point is too late, an operation speed characteristic of the semiconductor memory device may be degraded, and thus a sense amplification enable time point should be determined in light of the tradeoff between manufacturing yield and operation speed characteristic.
FIG. 1 is a block diagram illustrating a data output path of a conventional semiconductor memory device having a clocked regenerative amplifier. The semiconductor memory vice of FIG. 1 comprises a memory cell 10, a bit line sense amplifier 20, an I/O sense amplifier 30, a clocked regenerative amplifier 40, a previous-step output driving circuit 50, and an output driving circuit 60. The I/O sense amplifier 30 comprises a current amplifier 32 and a differential amplifier 34.
Functions of the components of the data output path of the semiconductor memory device of FIG. 1 are described below with reference to FIG. 1.
The memory cell 10 receives a row address to enable a word line WL, and the bit line sense amplifier 20 amplifies a voltage corresponding to a charge stored in a capacitor C of the memory cell 10.
The I/O sense amplifier 30 receives outputs of a bit line BL and a bit line bar BLB of the bit line sense amplifier 20 through a global I/O line pair GIO and GIOB to amplify a current level through the current amplifier 32 and the differential amplifier 34.
The clocked regenerative amplifier 40 receives output signals IN and INB of the I/O sense amplifier which do not have a power voltage level or a ground voltage level from the I/O sense amplifier 30 and outputs output signals Q and QB of a power voltage level and a ground voltage level in response to a state of the sense amplification enable signal SA_EN.
The previous-step output driving circuit 50 receives a positive output signal Q of a power voltage level and a negative output signal QB of a ground voltage level from the clocked regenerative amplifier 40 and delays them by a predetermined time before outputting them through a data line.
The output driving circuit 60 receives an output signal from the previous-step output driving circuit 50 and delays it by a predetermined time period before outputting buffered read data to a data I/O pin.
An operation of the data output path of the semiconductor memory device having the clocked regenerative amplifier according to the conventional art is described below with reference to FIG. 1.
When an NMOS transistor N in the memory cell 100 receives a row address through its gate to enable the word line WL, the NMOS transistor N is turned on, so that charge stored in the capacitor C is transmitted through the NMOS transistor N.
The bit line sense amplifier 20 receives charge stored in the capacitor C of the memory cell 10 in the form of an electric current through the bit line BL and the bit line bar BLB to firstly amplify a voltage corresponding thereto.
The I/O sense amplifier 30 receives voltage outputs of the bit line BL and the bit line bar BLB which are firstly amplified by the bit line sense amplifier 20 through the global I/O line pair GIO and GIOB, and secondly amplifies them at the current amplifier 32 and then thirdly amplifies them at the differential amplifier 34.
The clocked regenerative amplifier 40 receives the thirdly amplified voltage outputs which do not have a power voltage level or a ground voltage level from the I/O sense amplifier 30 and receives the sense amplification enable signal SA_EN through a clock signal input terminal, so that it is synchronized with the sense amplification enable signal SA_EN to output the output signals Q and QB of a power voltage level and a ground voltage level.
That is, the clocked regenerative amplifier 40 as the latch form does not operate when the sense amplification, enable signal SA_EN has a low level, and it receives the voltage outputs IN and INB of the I/O sense amplifier 30 which are thirdly amplified and does not have a power voltage level or a ground voltage level to generate in a short time, and output, the output signals Q and QB of a power voltage level and a ground voltage level by repetitive self amplification while the sense amplification enable signal SA_EN transitions to a high level and then maintains a high level.
The previous-step output driving circuit 50 receives the positive output signals and the negative output signals Q and QB which have a power voltage level and a ground voltage level from the clocked regenerative amplifier 40 and delaying them by a predetermined time before outputting them through the data line, and so the output driving circuit 60 receives the output signals and delays them by a predetermined time before outputting the buffered read data RD to the data I/O pin.
FIG. 2 is a dispersion graph illustrating a relationship between a sense amplification enable signal generating time point and a manufacturing yield for the conventional semiconductor memory device. In FIG. 2, a horizontal axis denotes the sense amplification enable signal generating time point, a vertical axis denotes dispersion of semiconductor memory devices manufactured, and the area below the dispersion curve line denotes the manufacturing yield.
An operation speed of the sense amplifier is in proportion to a generation time point of the sense amplification enable signal SA_EN, and thus the faster the generation time point of the sense amplification enable signal SA_EN, the faster the operation speed of the sense amplifier, whereas the slower the generation time point of the sense amplification enable signal SA_EN, the slower the operation speed of the sense amplifier.
The operation speed of the sense amplifier is in inverse proportion to the manufacturing yield, and thus the faster the operation speed of the sense amplifier, the lower the manufacturing yield of the semiconductor memory device, where manufacturing yield can be related to a ratio by which good quality dies are selected in a wafer test process.
Thus, semiconductor memory devices having a relatively fast generating time point of the sense amplification enable signal SA_EN have a relatively low manufacturing yield, whereas semiconductor memory device having a relatively slow generating time point of the sense amplification enable signal SA_EN have a relatively high manufacturing yield, so that a relation therebetween has dispersion of a normal distribution.
For example, assume that one million dies are produced from a semiconductor wafer. In a relatively low-speed semiconductor memory device in which the generating time point of the sense amplification enable signal SA_EN is 4 ns, up to 9 hundred thousand dies are determined to be passed as good quality, whereas in a relatively high-speed semiconductor memory device in which the generating time point of the sense amplification enable signal SA_EN is 3 ns, up to only 8 hundred thousand dies are determined to be passed as good quality.
Such discrepancy in yield can be caused from a mismatch such as an electrical parameter difference and a threshold voltage difference between the NMOS transistors in the sense amplifier and a capacitor difference between the bit line BL and the bit line bar BLB.
In order to resolve this discrepancy, since there is a restriction to setting the optimum generation time point of the sense amplification enable signal SA_EN for all dies on the semiconductor wafer, the low speed semiconductor memory device having a high manufacturing yield is first produced by giving priority to a manufacturing yield or otherwise the high speed semiconductor memory device having a low manufacturing yield is first produced by giving priority to an operation speed. That is, one of the two methods for determining priority should be selected.